1. Field of Invention
This invention relates in general to a method of forming an inter-layer dielectric (ILD) layer. More particularly, this invention is directed toward a method of planarizing a pre-metal dielectric (PMD) layer using a chemical-mechanical polishing (CMP) process.
2. Description of Related Art
In general, there are two types of dielectrics which are grouped under the title of inter-layer dielectric (ILD). The first type is a pre-metal dielectric (PMD), which refers generally to a dielectric material formed before a metallization process is performed. The PMD serves as an isolating layer between the semiconductor component and the first metallic layer. The second type of dielectric is an inter-metal dielectric (IMD), which is a dielectric layer interposed between two metallic layers for isolation.
Referring to FIGS. 1a and 1b, a conventional method of forming a PMD is shown. First, and referring to FIG. 1a, a semiconductor substrate 10, for example, a silicon substrate, having a semiconductor component 12 formed thereabove, is provided. The semiconductor component 12 is, for example, a MOS component having a gate and source/drain terminals. Thereafter, a PMD layer 14, for example, a borophosphosilicate glass (BPSG) layer formed using a chemical vapor deposition (CVD) method, is formed above the semiconductor substrate 10.
Referring next to FIG. 1b, the PMD layer 14 is subjected to a heat flow process using a high temperature between, for example, about 850.degree. C. and about 950.degree. C. Thus, the original undulating PMD layer 14, which generally followed the undulating profile of the semiconductor component 12, becomes smoother and somewhat planarized.
Although the heat flow process can smooth the profile of the PMD layer a little, the result is usually not sufficiently smooth. Therefore, additional techniques, such as applying a spin-on glass (SOG) coverage followed by an etching back procedure, often have to be used to provide the local planarization.
However, manufacturers are entering a sub-half micron manufacturing era. As such, in order to meet the processing window requirements for various processes, such as photolithography, etching and deposition, chemical-mechanical polishing (CMP) is generally used for global planarization. Hence, CMP is also used for the planarization of the aforementioned PMD layer.
Furthermore, after the planarization of the PMD layer, a pure oxide layer is typically formed, for example, a PE-OX (plasma enhanced chemical vapor deposition oxide) or a PE-TEOS (plasma-enhanced chemical vapor deposition tetraethylorthosilicate) layer, so as to cover up defects, such as scratches, formed during the CMP operation. Nevertheless, because of the thinning of the layer as a result of polishing, and due to the immersion in grinding fluids while undergoing the CMP operation, after the CMP operation is performed, the gettering effect for the PMD layer will be weakened. This will lead to a lower resistance for poly-loads in products that contain such items, for example, SRAMs, after the subsequent inter-metal dielectric formation, thereby causing production yield problems.